US Patent 11595064 Clock recovery and cable diagnostics for ethernet phy
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US Patent 11595064 Clock recovery and cable diagnostics for ethernet phy
Article
A receiver circuit includes an analog-to-digital converter (ADC), a decision feedback equalizer (DFE), a slicer, and a timing error detector (TED). The DFE is coupled to the ADC, and includes a first tap and a second tap. The slicer is coupled to the DFE. The TED is coupled to the slicer. The TED is configured to initialize timing of a sampling clock provided to the ADC while initializing the second tap of the DFE and holding the first tap of the DFE at a constant value.
Infobox
Is a
Patent Applicant
Current Assignee
Patent Jurisdiction
Patent Number
115950640
Date of Patent
February 28, 2023
0Patent Application Number
174013980
Date Filed
August 13, 2021
0Patent Citations
Patent Primary Examiner
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