US Patent 11599268 Storage device and method of operating the same

The present technology relates to an electronic device. According to the present technology, a storage device having an improved operation speed includes a memory device including a plurality of memory areas, a buffer memory configured to store first parity information including a parity for data stored in each of one or more first memory areas among the plurality of memory areas, and a memory controller configured to store second parity information including a parity for data stored in each of one or more second memory areas except for the one or more first memory areas among the plurality of memory areas and control the memory device to store, when a sudden power off occurs, dump parity information including some of the first parity information and the second parity information.