Patent attributes
An integrated circuit is provided, which includes: a processor, a general interrupt controller, and a bus master. The bus master includes: a bus-control circuit and a polling circuit, which is configured to detect whether an interrupt signal of the sensing device is asserted. In response to the polling circuit detecting that the interrupt signal is asserted, the bus-control circuits fetches each task stored in a task queue of a memory in sequence, and performs one or more data-transfer operations corresponding to each task to obtain sensor data from the sensing device. In response to a task-completion signal of the tasks generated by the bus-control circuit, the general interrupt controller generates an interrupt request signal. In response to the interrupt request signal, the processor reports a sensor event using the sensor data obtained by the data-transfer operations corresponding to each task.
