Is a
Patent attributes
Patent Applicant
Current Assignee
Patent Jurisdiction
Patent Number
Patent Inventor Names
Alper Genc0
Ravindranath D. Shrivastava0
Date of Patent
April 18, 2023
0Patent Application Number
174921800
Date Filed
October 1, 2021
0Patent Citations
...
Patent Citations Received
Patent Primary Examiner
A FET switch stack has a stacked arrangement of FET switches, a gate resistor network with ladder resistors and common gate resistors, and a gate resistor bypass arrangement. The bypass arrangement has a first set of bypass switches connected across the gate resistors and a second set of bypass switches connected across the ladder resistors. Bypass occurs during at least a portion of the transition state of the stacked arrangement of FET switches.
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