Patent attributes
An integrated circuit (IC) can include a plurality of circuit blocks, wherein each circuit block includes design for testability (DFT) circuitry. The DFT circuitry can include a scan interface, wherein each scan interface is uniform with the scan interface of each other circuit block of the plurality of circuit blocks, an embedded deterministic test circuit coupled to the scan interface, wherein the embedded deterministic test circuit couples to circuitry under test, and a scan response analyzer coupled to the scan interface. The scan response analyzer is configured to operate in a selected scan response capture mode selected from a plurality of scan response capture modes. The IC can include a global scan router connected to the scan interfaces of the plurality of circuit blocks. The global scan router is configured to activate a subset of the plurality of circuit blocks in parallel for a scan test.