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US Patent 11663381 Clock mapping in an integrated circuit design
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Patent
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Date Filed
September 7, 2021
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Date of Patent
May 30, 2023
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Patent Application Number
17468304
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Patent Citations
US Patent 8661383 VLSI black-box verification
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US Patent 8930863 System and method for altering circuit design hierarchy to optimize routing and power distribution using initial RTL-level circuit description netlist
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US Patent 10268797 Architectural physical synthesis
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US Patent 10372858 Design-for-testability (DFT) insertion at register-transfer-level (RTL)
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US Patent 10586003 Circuit design using high level synthesis and linked hardware description language libraries
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US Patent 10762265 Heterogeneous instantiation of high-level language callable library for hardware core
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US Patent 10796048 Adding delay elements to enable mapping a time division multiplexing circuit on an FPGA of a hardware emulator
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US Patent 10915683 Methodology to create constraints and leverage formal coverage analyzer to achieve faster code coverage closure for an electronic structure
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US Patent 10911323 System-on-chip (SoC) assembly, configurable IP generation and IP integration utilizing distributed computer systems
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US Patent 11010522 Efficient mechanism for interactive fault analysis in formal verification environment
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•••
Patent Citations Received
US Patent 12073156 Propagating physical design information through logical design hierarchy of an electronic circuit
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US Patent 11928409 Dynamic abstract generation and synthesis flow with area prediction
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Patent Jurisdiction
United States Patent and Trademark Office
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Patent Number
11663381
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Patent Primary Examiner
Jack Chiang
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CPC Code
G06F 30/327
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G06F 30/31
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G06F 30/323
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