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US Patent 11663391 Latch-up avoidance for sea-of-gates
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Patent
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Date Filed
August 25, 2021
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Date of Patent
May 30, 2023
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Patent Application Number
17411113
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Patent Citations
US Patent 10509878 Systems and methods for routing track assignment
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US Patent 7696541 Structure for a latchup robust gate array using through wafer via
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US Patent 7102867 Method, apparatus and circuit for latchup suppression in a gate-array ASIC environment
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Patent Jurisdiction
United States Patent and Trademark Office
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Patent Number
11663391
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Patent Primary Examiner
Jack Chiang
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CPC Code
G06F 30/394
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H01L 27/0207
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