Patent attributes
A dynamic random-access memory array includes a plurality of memory cells and sensor cells physical arranged in a row. The sensor cells include a transistor and a capacitor having an input terminal connected to a first non-gate terminal of the transistor. A wordline is connected to transistor gates of both the memory cells and sensor cells in the row. A sensor amplifier has inputs connected to the sensor cell, a high voltage reference line, and a low voltage reference line, and an output in communication with a row refresh circuit. If the sensor amplifier detects that the sensor cell voltage falls outside of the range of the high and low voltage reference lines, then a trigger signal is output to request that the row refresh circuit perform a priority row refresh of the memory cells and the sensor cell in the row.
