US Patent 11682461 Memory cell arrangement and methods thereof

A memory cell arrangement is provided that may include: a plurality of first control lines; a plurality of second control lines; a plurality of third control lines; each of a plurality of memory cell sets includes memory cells and is assigned to a corresponding one of the plurality of first control lines and includes at least a first memory cell subset addressable via the corresponding first control line, a corresponding one of the plurality of second control lines, and the plurality of third control lines, and at least a second memory cell subset addressable via the corresponding first control line, the plurality of second control lines, and a corresponding one of the plurality of third control lines. The corresponding one of the plurality of third control lines addresses the second memory cell subset of each memory cell set of the plurality of memory cell sets.