US Patent 11693794 Tunable and scalable command/address protocol for non-volatile memory

A data storage system includes a storage medium including a plurality of memory cells; a storage controller in communication with the storage medium; and an electrical interface between the storage medium and the storage controller. The electrical interface includes an N-bit data bus; a data strobe; a command latch enable signal; and an address latch enable signal; wherein, while the command latch signal or the address latch enable signal is asserted, the storage medium is configured to: (i) receive command or address data via a subset of lines of the data bus; and (ii) latch the command or address data using the data strobe.