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US Patent 11694935 Systems and methods for wafer-level photonic testing

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
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Current Assignee
Ayar Labs, Inc.
Ayar Labs, Inc.
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Date Filed
October 23, 2020
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Date of Patent
July 4, 2023
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Patent Applicant
Ayar Labs, Inc.
Ayar Labs, Inc.
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Patent Application Number
17079357
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Patent Citations
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US Patent 10845555 Optical module and associated methods
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US Patent 11163120 Fiber attach enabled wafer level fanout
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US Patent 11137548 Retro reflector and associated methods
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US Patent 9690042 Optical input/output device, optical electronic system including the same, and method of manufacturing the same
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US Patent 10012798 Sacrificial coupler for testing V-grooved integrated circuits
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US Patent 10145758 Wafer level optical probing structures for silicon photonics
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US Patent 10330875 Optical module and associated methods
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US Patent 10359567 Test systems and methods for chips in wafer scale photonic systems
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
11694935
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Patent Primary Examiner
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Jerry Rahll
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