US Patent 11709521 Synchronous clock domain crossing skew optimization and multi-clock buffer (MBUFG)

Synthetizing a hardware description language code into a netlist comprising loads and a multi-clock buffer (MBUF). The MBUF receives a global clocking signal and generates a first and a second related clocking signals. The loads are grouped into a first and a second groups receiving the first and the second clocking signals respectively. A first/second clock modifying leaf are placed between a common node and the first/group groups respectively, wherein the common node is positioned closer in proximity to the first/second groups in comparison to a clock source generating the global clocking signal. The first/second clock modifying leaves receive a least divided clocking signal from the MBUF and generate the first/second clocking signals respectively. The least divided clocking signal is routed from the MBUF to the first/second clock modifying leaves. The first/second clocking signals are routed from the first/second clock modifying leaves to the first/second group respectively.