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US Patent 11716847 Three-dimensional NAND memory device with split gates

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
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Date Filed
December 7, 2020
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Date of Patent
August 1, 2023
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Patent Application Number
17113624
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Patent Citations
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US Patent 9754963 Multi-tier memory stack structure containing two types of support pillar structures
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US Patent 9853050 Semiconductor memory device and method for manufacturing the same
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US Patent 10068917 Vertical memory devices and methods of manufacturing the same
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US Patent 10090318 Vertical string of memory cells individually comprising a programmable charge storage transistor comprising a control gate and a charge storage structure and method of forming a vertical string of memory cells individually comprising a programmable charge storage transistor comprising a control gate and a charge storage structure
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US Patent 10103165 Memory device
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US Patent 10497711 Non-volatile memory with reduced program speed variation
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US Patent 10276583 Three-dimensional memory device containing composite word lines including a metal silicide and an elemental metal and method of making thereof
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US Patent 10566346 Vertical-type memory device
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US Patent 8921921 Nonvolatile memory device and method for fabricating the same
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US Patent 9305849 Method of making a three dimensional NAND device
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
11716847
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Patent Primary Examiner
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Mary A Wilczewski
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CPC Code
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H01L 27/11529
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H01L 23/5226
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H01L 29/40117
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H01L 29/4234
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G11C 16/0483
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H01L 27/11524
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