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US Patent 11748625 Distributed convolution for neural networks

Patent 11748625 was granted and assigned to Intel on September, 2023 by the United States Patent and Trademark Office.

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Contents

Is a
Patent
Patent

Patent attributes

Patent Applicant
Intel
Intel
Current Assignee
Intel
Intel
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
11748625
Patent Inventor Names
Carey K. Kloss
Amir Khosrowshahi
Aravind Kalaiah
Vijay Anand R. Korthikanti
Tony L. Werner
Date of Patent
September 5, 2023
Patent Application Number
15395675
Date Filed
December 30, 2016
Patent Citations
‌
US Patent 10198401 Max pooling in a matrix processing architecture
‌
US Patent 10922380 Distributed matrix multiplication for neural networks
‌
US Patent 10228937 Programmable matrix processing engine
‌
US Patent 7483932 Method and system for computing multidimensional fast Fourier transforms
‌
US Patent 7730121 Parallel processing systems and method
‌
US Patent 8356086 Distributed non-negative matrix factorization
‌
US Patent 9424076 Dynamic distribution for distributed arrays and related rules
‌
US Patent 10169296 Distributed matrix multiplication for neural networks
Patent Citations Received
‌
US Patent 12124360 Setting method of in-memory computing simulator
0
Patent Primary Examiner
‌
Viker A Lamardo
CPC Code
‌
G06N 3/063
‌
G06N 20/00
‌
G06N 3/08
‌
G06N 3/04
‌
G06N 3/082

In one embodiment, a matrix operation may be performed using a plurality of input matrices, wherein the matrix operation is associated with one or more convolution operations. The plurality of input matrices may be partitioned into a plurality of input partitions, wherein the plurality of input matrices is partitioned based on a number of available processing elements. The plurality of input partitions may be distributed among a plurality of processing elements, wherein each input partition is distributed to a particular processing element of the plurality of processing elements. A plurality of partial matrix operations may be performed using the plurality of processing elements, and partial matrix data may be transmitted between the plurality of processing elements while performing the plurality of partial matrix operations. A result of the matrix operation may be determined based on the plurality of partial matrix operations.

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