US Patent 11755491 Mapping supporting non-sequential writes at sequentially-written memory devices

A system includes integrated circuit (IC) dice having memory cells and a processing device coupled to the IC dice. The processing device is to perform operations including: causing a logic to enter an initial state associated with a first group of memory cells in response to an input-output (IO) write request directed at the first group of memory cells; retrieving a write pointer that includes a location within the first group of memory cells; causing the logic to transition from the initial state to a sequential IO state; and in response to determining the IO write request is directed to the location of the write pointer, causing data of the IO write request to be written to the plurality of IC dice starting at the location of the write pointer.