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US Patent 11762014 3D TAP and scan port architectures

Patent 11762014 was granted and assigned to Texas Instruments on September, 2023 by the United States Patent and Trademark Office.

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Is a

Patent attributes

Patent Applicant

Texas Instruments

Current Assignee

Texas Instruments

Patent Jurisdiction

United States Patent and Trademark Office

Patent Number

Patent Inventor Names

Lee D. Whetsel

Date of Patent

September 19, 2023

Patent Application Number

18094522

Date Filed

January 9, 2023

Patent Citations

US Patent 8793547 3D built-in self-test scheme for 3D assembly defect detection

US Patent 8924802 IC TAP with dual port router and additional capture input

US Patent 8977919 Scan, test, and control circuits coupled to IC surfaces contacts

US Patent 9229056 IC die top, bottom signals, tap lock, test, scan circuitry

US Patent 9417284 IC die with tap lock, test, scan, and up circuitry

US Patent 9535126 Tap, test, CSU, scan circuitry with top and bottom contacts

US Patent 9720039 Interleaver ic with up control and capture, shift, update circuitry

US Patent 10012695 Die top, bottom parallel/serial date with test and scan circuitry

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Patent Primary Examiner

John J Tabone, Jr.

CPC Code

...

Patent abstract

This disclosure describes die test architectures that can be implemented in a first, middle and last die of a die stack. The die test architectures are mainly the same, but for the exceptions mentioned in this disclosure.

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