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US Patent 11762302 Integrated circuit overlay test patterns and method thereof

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
Date Filed
May 24, 2021
Date of Patent
September 19, 2023
Patent Application Number
17327990
Patent Citations
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US Patent 9093530 Fin structure of FinFET
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US Patent 9134633 System and method for dark field inspection
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US Patent 9230867 Structure and method for E-beam in-chip overlay mark
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US Patent 9304403 System and method for lithography alignment
‌
US Patent 9404743 Method for validating measurement data
‌
US Patent 9823585 EUV focus monitoring systems and methods
‌
US Patent 9548303 FinFET devices with unique fin shape and the fabrication thereof
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US Patent 9841687 Synchronized integrated metrology for overlay-shift reduction
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US Patent 8796666 MOS devices with strain buffer layer and methods of forming the same
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US Patent 8837810 System and method for alignment in semiconductor device fabrication
Patent Inventor Names
Yueh-Yi Chen
Kung-Cheng Lin
Chih-Ting Sun
Ying-Jung Chen
Tseng Chin Lo
Meng Lin Chang
Bo-Sen Chang
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
11762302
Patent Primary Examiner
‌
Duy T Nguyen
CPC Code
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H01L 22/34
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H01L 23/544
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H01L 2223/54426
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G06F 30/392
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H01L 22/24
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H01L 21/68
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H01L 22/30
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H01L 29/785
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H01L 22/12
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G03F 1/44
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