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US Patent 11762789 Integrated circuit I/O integrity and degradation monitoring

Overview Structured Data Issues Contributors Activity

Is a

Date Filed

January 31, 2022

Date of Patent

September 19, 2023

Patent Application Number

17589758

Patent Citations

US Patent 7701246 Programmable delay line compensated for process, voltage, and temperature

US Patent 9490787 System and method for integrated circuit clock distribution

US Patent 9536038 Method and algorithm for functional critical paths selection and critical path sensors and controller insertion

US Patent 9564883 Circuitry and method for timing speculation via toggling functional critical paths

US Patent 9564884 Circuitry and method for measuring negative bias temperature instability (NBTI) and hot carrier injection (HCI) aging effects using edge sensitive sampling

US Patent 9632126 Circuit of measuring leakage current in a semiconductor integrated circuit

US Patent 9714966 Circuit aging sensor

US Patent 9760672 Circuitry and method for critical path timing speculation to enable process variation compensation via voltage scaling

US Patent 9791834 Fast digital to time converter linearity calibration to improve clock jitter performance

US Patent 9954455 Constant on time COT control in isolated converter

•••

Patent Inventor Names

Eyal Fayneh

Shai Cohen

Guy Redler

Evelyn Landman

Inbar Weintrob

Patent Jurisdiction

United States Patent and Trademark Office

Patent Number

Patent Primary Examiner

Tammara R Peyton

CPC Code

H01L 2224/16227

H01L 2924/15321

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