US Patent 11764146 Microelectronic devices with self-aligned interconnects, and related methods

Methods for forming microelectronic device structures include forming interconnects that are self-aligned with both a lower conductive structure and an upper conductive structure. At least one lateral dimension of an interconnect is defined upon subtractively patterning the lower conductive structure along with a first sacrificial material. At least one other lateral dimension of the interconnect is defined by patterning a second sacrificial material or by an opening formed in a dielectric material through which the interconnect will extend. A portion of the first sacrificial material, exposed within the opening through the dielectric material, along with the second sacrificial material are removed and replaced with conductive material(s) to integrally form the interconnect and the upper conductive structure. The interconnect occupies a volume between vertically overlapping areas of the lower conductive structure and the upper conductive structure, where such overlapping areas coincide with the opening through the dielectric material.