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US Patent 11768798 Multi-level hierarchical routing matrices for pattern-recognition processors

Patent 11768798 was granted and assigned to Micron Technology on September, 2023 by the United States Patent and Trademark Office.

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 US Patent 11768798 Multi-level hierarchical routing matrices for pattern-recognition processors

Article

Patent abstract

Multi-level hierarchical routing matrices for pattern-recognition processors are provided. One such routing matrix may include one or more programmable and/or non-programmable connections in and between levels of the matrix. The connections may couple routing lines to feature cells, groups, rows, blocks, or any other arrangement of components of the pattern-recognition processor.

Infobox
Is a
Patent
Patent
Patent Applicant
Micron Technology
Micron Technology
Current Assignee
Micron Technology
Micron Technology
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
11768798
Patent Inventor Names
David R. Brown
Harold B Noyes
Date of Patent
September 26, 2023
Patent Application Number
17550593
Date Filed
December 14, 2021
Patent Citations
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US Patent 7089352 CAM modified to be used for statistic calculation in network switches and routers
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US Patent 7146643 Intrusion detection accelerator
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US Patent 7176717 Programmable logic and routing blocks with dedicated lines
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US Patent 7276934 Integrated circuit with programmable routing structure including diagonal interconnect lines
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US Patent 7305047 Automatic lane assignment for a receiver
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US Patent 7358761 Versatile multiplexer-structures in programmable logic using serial chaining and novel selection schemes
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US Patent 7366352 Method and apparatus for performing fast closest match in pattern recognition
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US Patent 7392229 General purpose set theoretic processor
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US Patent 7428722 Versatile multiplexer-structures in programmable logic using serial chaining and novel selection schemes
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US Patent 7487131 General Purpose set theoretic processor
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US Patent 7487542 Intrusion detection using a network processor and a parallel pattern detection engine
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US Patent 7499464 Buffered crossbar switch with a linear buffer to port relationship that supports cells and packets of variable size
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US Patent 7725510 Method and system for multi-character multi-pattern pattern matching
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US Patent 7774286 GPSTP with multiple thread functionality
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US Patent 7804719 Programmable logic block having reduced output delay during RAM write processes when programmed to function in RAM mode
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US Patent 7890923 Configurable pattern detection method and apparatus
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US Patent 7899052 Memory structure for resolving addresses in a packet-based network switch
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US Patent 7916510 Reformulating regular expressions into architecture-dependent bit groups
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US Patent 7917684 Bus translator
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US Patent 7970964 Methods and systems to accomplish variable width data input
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US Patent 8020131 Method and apparatus for mapping flip-flop logic onto shift register logic
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US Patent 8065249 GPSTP with enhanced aggregation functionality
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US Patent 8140780 Systems, methods, and devices for configuring a device
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US Patent 8146040 Method of evaluating an architecture for an integrated circuit device
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US Patent 8159900 Acoustic system quality assurance and testing
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US Patent 8209521 Methods of indirect register access including automatic modification of a directly accessible address register
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US Patent 8214672 Method and systems for power consumption management of a pattern-recognition processor
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US Patent 8536896 Programmable interconnect element and method of implementing a programmable interconnect element
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US Patent 8593175 Boolean logic in a state machine lattice
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US Patent 8648621 Counter operation in a state machine lattice
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US Patent 8680888 Methods and systems for routing in a state machine
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US Patent 8725961 Systems, methods, and devices for configuring a device
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US Patent 8782624 Methods and systems for detection in a state machine
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US Patent 8843523 Devices, systems, and methods for communicating pattern matching results of a parallel pattern search engine
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US Patent 8938590 Indirect register access method and system
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US Patent 9058465 Counter operation in a state machine lattice
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US Patent 9063532 Instruction insertion in state machine engines
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US Patent 9075428 Results generation for state machine engines
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US Patent 9118327 Boolean logic in a state machine lattice
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US Patent 9164945 Devices, systems, and methods to synchronize parallel processing of a single data stream
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US Patent 9235798 Methods and systems for handling data received by a state machine engine
Patent Primary Examiner
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Michael J Metzger
CPC Code
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G06F 15/80

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