Patent attributes
A semiconductor chip is provided. The semiconductor chip includes a SRAM cell, a logic cell, a signal line and a ground line. The SRAM cell includes a storage transmission gate, a read transmission gate and a latch circuit. The latch circuit is serially connected between the storage and read transmission gates, and includes a first inverter, a second inverter and a transmission gate connected to an output of the first inverter, an input of the second inverter and an output of the storage transmission gate. The logic cell disposed aside the SRAM cell is connected with the SRAM cell by first and second active structures. The signal and ground lines extend at opposite sides of the SRAM and logic cells, and are substantially parallel with the first and second active structures. The SRAM and logic cells are disposed between and electrically connected to the signal and ground lines.
