Patent attributes
A method for semiconductor metrology includes depositing a first film layer on a semiconductor substrate and a second film layer overlying the first film layer. The first and second film layers are patterned to define a plurality of overlay targets comprising first target features formed in the first film layer having respective first locations, which are spaced apart by first nominal distances, and second target features formed in the second film layer having respective second locations, which are spaced apart by second nominal distances, which are different from the first nominal distances. An image of the semiconductor substrate is processed to measure respective displacements between the first and second target locations in each of the overlay targets, and to estimate both an actual overlay error between the patterning of the first and second film layers and a measurement error of the imaging assembly.
