US Patent 11775213 Stacked memory device with paired channels

A stacked memory device includes memory dies over a base die. The base die includes separate memory channels to the different dies and external channels that allow an external processor access to the memory channels. The base die allows the external processor to access multiple memory channels using more than one external channel. The base die also allows the external processor to communicate through the memory device via the external channels, bypassing the memory channels internal to the device. This bypass functionality allows the external processor to connect to additional stacked memory devices.