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US Patent 11775332 Technologies for memory replay prevention using compressive encryption

Patent 11775332 was granted and assigned to Intel on October, 2023 by the United States Patent and Trademark Office.

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Is a
Patent
Patent

Patent attributes

Patent Applicant
Intel
Intel
Current Assignee
Intel
Intel
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
11775332
Patent Inventor Names
Siddhartha Chhabra
David M. Durham
Michael E. Kounavis
Date of Patent
October 3, 2023
Patent Application Number
17532886
Date Filed
November 22, 2021
Patent Citations
‌
US Patent 9621241 Method for transmitting channel state information and apparatus therefor
‌
US Patent 7827218 Deterministic lookup using hashed key in a multi-stride compressed trie structure
‌
US Patent 7962638 Data stream filters and plug-ins for storage managers
‌
US Patent 8180741 Methods and systems for providing data objects on a token
‌
US Patent 9159419 Non-volatile memory interface
‌
US Patent 10268593 Block store managamement using a virtual computing system service
Patent Primary Examiner
‌
Venkat Perungavoor
Patent abstract

Systems and methods for memory isolation are provided. The methods include receiving a request to write a data line to a physical memory address, where the physical memory address includes a key identifier, selecting an encryption key from a key table based on the key identifier of the physical memory address, determining whether the data line is compressible, compressing the data line to generate a compressed line in response to determining that the data line is compressible, where the compressed line includes compression metadata and compressed data, adding encryption metadata to the compressed line, where the encryption metadata is indicative of the encryption key, encrypting a part of the compressed line with the encryption key to generate an encrypted line in response to adding the encryption metadata, and writing the encrypted line to a memory device at the physical memory address. Other embodiments are described and claimed.

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