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US Patent 11782679 Multiplexing between different processing channels

Patent 11782679 was granted and assigned to Imagination Technologies on October, 2023 by the United States Patent and Trademark Office.

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Contents

Is a
Patent
Patent

Patent attributes

Patent Applicant
Imagination Technologies
Imagination Technologies
Current Assignee
Imagination Technologies
Imagination Technologies
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
11782679
Patent Inventor Names
Kenneth C. Rovers
Date of Patent
October 10, 2023
Patent Application Number
17844169
Date Filed
June 20, 2022
Patent Citations
‌
US Patent 9317475 Multiplexing auxiliary processing element and semiconductor integrated circuit
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US Patent 9959247 Permuting in a matrix-vector processor
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US Patent 9966960 Configurable logic circuit including dynamic lookup table
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US Patent 10521226 Efficient implementation of complex vector fused multiply add and complex vector multiply
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US Patent 10942985 Apparatuses, methods, and systems for fast fourier transform configuration and computation instructions
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US Patent 7242216 Embedding memory between tile arrangement of a configurable IC
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US Patent 7526632 System, apparatus and method for implementing multifunctional memory in reconfigurable data path processing
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US Patent 7636835 Coupling data in a parallel processing environment
...
Patent Primary Examiner
‌
Eric Coleman
Patent abstract

A circuit for use in a processor includes a first processing channel having a first logic unit, a second processing channel having a second logic unit, and multiplexing circuitry. The multiplexing circuitry includes an input multiplexer arranged to switch between a first state in which an input of the first logic unit is coupled to an input line of the first processing channel, and a respective second state in which the input of the first logic unit is instead coupled to an input line of the second processing channel; and an output multiplexer arranged to switch between a first state in which an output line of the second processing channel is coupled to an output of the second logic unit, and a second state in which the output line of the second processing channel is instead coupled to an output of the first logic unit.

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