US Patent 11789815 Memory controller and memory device including the same

A memory device includes; a memory module including a memory array, and a memory controller that retrieves read data from memory cells of the memory array. The memory controller includes a fault detector that detects faulty addresses associated with faulty memory cells among the memory cells providing data errors. The fault detector includes; a first inverter that generates inverted read data by reading and inverting the read data, wherein the inverted read data is stored in the memory array, a first buffer that stores the read data and provides buffered data, an XOR operator that receives the buffered data from the first buffer, receives read-out inverted data generated by reading the inverted read data stored in the memory array, and performs an XOR operation on the buffered data and the read-out inverted read data to generate calculation data, a fault address detection unit that identifies the faulty addresses in response to the calculation data and generates faulty address information, a second inverter that generates inverted read-out inverted read data by receiving and inverting the read-out inverted read data, and an error pattern change unit that converts an uncorrectable error (UE)-causing data into a correctable error (CE)-causing data.