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US Patent 11791299 Redistribution layer (RDL) layouts for integrated circuits
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Patent
Date Filed
April 27, 2018
Date of Patent
October 17, 2023
Patent Application Number
15965116
Patent Citations
US Patent 8956951 Method for manufacturing SOI wafer
US Patent 10014340 Stacked SPAD image sensor
US Patent 9153565 Image sensors with a high fill-factor
US Patent 10109487 Method for bonding substrates
US Patent 8242543 Semiconductor wafer-to-wafer bonding for dissimilar semiconductor dies and/or wafers
US Patent 8829657 Semiconductor substrate, semiconductor chip having the same, and stacked semiconductor package
Patent Inventor Names
Cheng-Yuan Li
Kuo-Cheng Lee
Yen-Liang Lin
Yun-Wei Cheng
Patent Jurisdiction
United States Patent and Trademark Office
Patent Number
11791299
Patent Primary Examiner
Nduka E Ojeh
CPC Code
H01L 2224/24145
H01L 2224/82896
H01L 2224/211
H01L 24/82
H01L 23/5389
H01L 24/24
H01L 24/20
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