US Patent 11791826 Clock recovery circuit for display

The present disclosure discloses a clock recovery circuit for a display, which recovers a clock from a clock data signal. The clock recovery circuit includes a clock recoverer configured to generate delayed clocks using a multi-stage delay chain including delay units; and a delay compensator configured to control a first delay time of a first delay unit to be the same as a second delay time of remaining delay units. The clock recovery circuit may compensate for a difference in delay time between the first delay time and the second delay time.