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US Patent 11791978 Systems and methods for preventing side-channel attacks

Patent 11791978 was granted and assigned to Georgia Tech Research Corporation on October, 2023 by the United States Patent and Trademark Office.

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Contents

Is a
Patent
Patent

Patent attributes

Patent Applicant
‌
Georgia Tech Research Corporation
Current Assignee
‌
Georgia Tech Research Corporation
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
11791978
Patent Inventor Names
Moinuddin Qureshi
Date of Patent
October 17, 2023
Patent Application Number
17270259
Date Filed
August 29, 2019
Patent Citations
‌
US Patent 9262342 Process authenticated memory page encryption
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US Patent 9342256 Epoch based storage management for a storage device
‌
US Patent 9767318 Secure controller systems and associated methods thereof
‌
US Patent 9990249 Memory integrity with error detection and correction
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US Patent 10311229 Mitigating timing side-channel attacks by obscuring alternatives in code
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US Patent 10585809 Convolutional memory integrity
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US Patent 10706164 Crypto-enforced capabilities for isolation
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US Patent 10846279 Transactional key-value store
...
Patent Citations Received
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US Patent 11972034 Hardware-assisted obscuring of cache access patterns
0
Patent Primary Examiner
‌
Sharon S Lynch
CPC Code
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G06F 2212/401
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G06F 7/588
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G06F 2212/1052
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G06F 12/084
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H04L 9/0625
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H04L 9/0631
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H04L 9/14
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H04L 9/005
...
Patent abstract

Disclosed herein is a method of accessing a cache, the method comprising: mapping respective physical line addresses (PLAs) of a plurality of PLAs to respective cache locations of a plurality of cache locations in a cache, each PLA of the plurality of PLAs having an associated memory line; encrypting, with a block cipher using a first key, a first PLA of the plurality of PLAs to provide a first encrypted line address (ELA), the first ELA having an associated first encrypted cache location; upon receiving a request to access a first memory line associated with the first PLA, encrypting, using the first key, the first PLA into the first ELA to determine the associated first encrypted cache location; and accessing the first encrypted cache location. Also disclosed herein are systems for implementing the same.

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