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US Patent 11805026 Channel training using a replica lane

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
Date Filed
August 14, 2020
Date of Patent
October 31, 2023
Patent Application Number
16993678
Patent Citations
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US Patent 8307265 Interconnection techniques
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US Patent 8760946 Method and apparatus for memory access delay training
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US Patent 9036757 Post-cursor locking point adjustment for clock data recovery
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US Patent 9030341 Compensation for lane imbalance in a multi-lane analog-to-digital converter (ADC)
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US Patent 10749756 Channel training using a replica lane
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US Patent 7467056 Method and apparatus for aligning multiple outputs of an FPGA
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US Patent 7500131 Training pattern based de-skew mechanism and frame alignment
Patent Inventor Names
Stanley Ames Lackey, Jr.
Edoardo Prete
Damon Tohidi
Gerald R. Talbot
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
11805026
Patent Primary Examiner
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Chae S Lee
CPC Code
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H04L 25/14
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H04L 43/0852
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H04L 7/10
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H04L 41/147
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H04L 43/50
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H04L 43/0823

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