Patent attributes
According to one embodiment, a memory controller controls a plurality of non-volatile memory chips. The memory controller includes a memory that stores first data and a processing unit that processes the first data stored in the memory. During a write operation, the processing unit generates second data including the first data and additional data corresponding to the first data, changes the bit order of the second data based on information indicating the state of the write destination of the second data, and writes the second data having the changed bit order to the plurality of non-volatile memory chips. During a read operation, the processing unit reads the second data having the changed bit order from the plurality of non-volatile memory chips and revert the bit order of the read second data to the original state based on the information.
