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US Patent 11837645 Method of manufacturing a semiconductor device
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Patent
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Date Filed
December 21, 2022
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Date of Patent
December 5, 2023
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Patent Application Number
18085871
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Patent Citations
US Patent 7696092 Method of using ternary copper alloy to obtain a low resistance and large grain size interconnect
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US Patent 7868456 Semiconductor device and method for fabricating the same
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US Patent 8211797 Metal wiring layer and method of fabricating the same
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US Patent 8778797 Systems and methods for selective tungsten deposition in vias
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US Patent 9082791 Method of forming low-resistance wire and method of manufacturing thin film transistor using the same
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US Patent 9082824 Method for forming an electrical connection between metal layers
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US Patent 10256342 Methods of manufacturing fin field effect transistors (FinFETs) comprising reduced gate thicknesses overlying deep trenches
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US Patent 10340219 Semiconductor device having a metal via
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US Patent 11393756 Methods of forming microelectronic devices, and related microelectronic devices, memory devices, and electronic systems
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US Patent 10734280 Integrated circuit devices and method of manufacturing the same
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•••
Patent Inventor Names
Heonbok Lee
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Wandon Kim
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Yoontae Hwang
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Geunwoo Kim
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Hanki Lee
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Taegon Kim
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Patent Jurisdiction
United States Patent and Trademark Office
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Patent Number
11837645
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Patent Primary Examiner
Earl N Taylor
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CPC Code
H01L 23/485
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H01L 23/5226
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H01L 23/53266
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H01L 29/0673
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H01L 29/0847
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H01L 29/41766
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H01L 29/41791
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H01L 29/42392
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H01L 29/456
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H01L 29/66795
0
•••
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