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US Patent 11861429 Resistive and digital processing cores

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
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Date Filed
April 30, 2018
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Date of Patent
January 2, 2024
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Patent Application Number
17049031
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Patent Citations
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US Patent 8959136 Matrix operations in an integrated circuit device
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US Patent 9143134 Combined analog architecture and functionality in a mixed-signal array
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US Patent 9152827 Apparatus for performing matrix vector multiplication approximation using crossbar arrays of resistive memory devices
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US Patent 9191241 Method for acquiring and processing signals
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US Patent 9640256 Nonvolatile static random access memory (NVSRAM) system having a static random access memory (SRAM) array and a resistive memory array
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US Patent 9847125 Resistive memory accelerator
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US Patent 9715655 Method and apparatus for performing close-loop programming of resistive memory devices in crossbar array based hardware circuits and systems
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US Patent 9910827 Vector-matrix multiplications involving negative values
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US Patent 7912889 Mapping the threads of a CTA to the elements of a tile for efficient matrix multiplication
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US Patent 8836708 Device for the parallel processing of a data stream
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Patent Inventor Names
Sai Rahul Chalamalasetti
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John Paul Strachan
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Martin Foltin
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Dejan S. Milojicic
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Amit S. Sharma
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
11861429
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Patent Primary Examiner
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Matthew D Sandifer
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CPC Code
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G06J 1/00
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G06F 17/16
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G06G 7/22
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