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US Patent 11862452 Contact isolation in semiconductor devices

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
0
Date Filed
August 28, 2020
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Date of Patent
January 2, 2024
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Patent Application Number
17006642
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Patent Citations
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US Patent 10079145 Method for pattern formation on a substrate, associated semiconductor devices, and uses of the method
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US Patent 9837414 Stacked complementary FETs featuring vertically stacked horizontal nanowires
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US Patent 10256158 Insulated epitaxial structures in nanosheet complementary field effect transistors
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US Patent 9576858 Dual work function integration for stacked FinFET
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US Patent 9659963 Contact formation to 3D monolithic stacked FinFETs
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Patent Inventor Names
Boon Teik Chan
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Waikin Li
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Zheng Tao
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
11862452
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Patent Primary Examiner
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Michael M Trinh
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CPC Code
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H01L 27/092
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H01L 27/0688
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H01L 21/8221
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H01L 21/823814
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H01L 21/823871
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H01L 21/823878
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H01L 29/0653
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H01L 29/775
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H01L 29/1079
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H01L 29/66439
0
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