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US Patent 11869812 Stacked complementary field effect transistors
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Patent
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Date Filed
September 1, 2021
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Date of Patent
January 9, 2024
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Patent Application Number
17463878
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Patent Citations
US Patent 8642416 Method of forming three dimensional integrated circuit devices using layer transfer technique
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US Patent 9219005 Semiconductor system and device
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US Patent 10192819 Integrated circuit structure incorporating stacked field effect transistors
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US Patent 10192867 Complementary FETs with wrap around contacts and method of forming same
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US Patent 10256158 Insulated epitaxial structures in nanosheet complementary field effect transistors
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US Patent 10304833 Method of forming complementary nano-sheet/wire transistor devices with same depth contacts
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US Patent 10388569 Formation of stacked nanosheet semiconductor devices
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US Patent 10381438 Vertically stacked NFETS and PFETS with gate-all-around structure
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US Patent 10483166 Vertically stacked transistors
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US Patent 8273610 Method of constructing a semiconductor device and structure
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•••
Patent Inventor Names
Alexander Reznicek
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Miaomiao Wang
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Huimei Zhou
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Ruilong Xie
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Patent Jurisdiction
United States Patent and Trademark Office
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Patent Number
11869812
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Patent Primary Examiner
Thinh T Nguyen
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CPC Code
H01L 29/66439
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H01L 29/42392
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H01L 21/84
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H01L 27/1203
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H01L 29/775
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