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US Patent 11874605 Verification metrology targets and their design

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
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Date Filed
July 6, 2020
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Date of Patent
January 16, 2024
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Patent Application Number
16921880
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Patent Citations
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US Patent 6985618 Overlay marks, methods of overlay mark design and methods of overlay measurements
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US Patent 7346878 Apparatus and methods for providing in-chip microtargets for metrology or inspection
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US Patent 7478019 Multiple tool and structure analysis
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US Patent 7561282 Techniques for determining overlay and critical dimension using a single metrology tool
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US Patent 7608468 Apparatus and methods for determining overlay and uses of same
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US Patent 7804994 Overlay metrology and control method
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US Patent 7933026 High resolution monitoring of CD variations
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US Patent 8214771 Scatterometry metrology target design optimization
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US Patent 8930156 Metrology through use of feed forward feed sideways and measurement cell re-use
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US Patent 9291554 Method of electromagnetic modeling of finite structures and finite illumination for metrology and inspection
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•••
Patent Citations Received
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US Patent 12092966 Device feature specific edge placement error (EPE)
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Patent Inventor Names
Mark Ghinovker
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Michael E. Adel
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Shiming Wei
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Inna Tarshish-Shapir
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
11874605
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Patent Primary Examiner
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Nghia M Doan
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CPC Code
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H01L 22/30
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G06F 30/00
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G03F 7/70616
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G03F 7/70491
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