US Patent 11875864 Mitigating edge layer effect in partially written blocks
Patent 11875864 was granted and assigned to Petaio on January, 2024 by the United States Patent and Trademark Office.
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US Patent 11875864 Mitigating edge layer effect in partially written blocks
Article
Patent abstract
A storage device includes 3D NAND including layers of multi-level cells. When a shutdown command is received, whether a block is partially written is evaluated. If so, dummy lines are written after the last written wordline of the block. Partially written blocks may be those having a fill percentage less than a threshold. The threshold may be a function of the PEC count of the block. If a maximum retention time is exceeded by data stored in a partially written block, dummy lines may also be written to the block.
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Patent Applicant
Current Assignee
Patent Jurisdiction
Patent Number
Patent Inventor Names
Chengxu Zhang0
LingQi Zeng0
Naveen Kumar0
Seok Lee0
Date of Patent
January 16, 2024
0Patent Application Number
174995710
Date Filed
October 12, 2021
0Patent Citations
Patent Primary Examiner
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