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US Patent 11881271 Non-volatile memory with engineered channel gradient

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
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Date Filed
May 31, 2022
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Date of Patent
January 23, 2024
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Patent Application Number
17828685
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Patent Citations
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US Patent 9747992 Non-volatile memory with customized control of injection type of disturb during read operations
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US Patent 10210941 Reducing injection type of read disturb in a cold read of a memory device
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US Patent 10217518 Reducing hot electron injection type of read disturb in 3D memory device having connected source-end select gates
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US Patent 10235294 Pre-read voltage pulse for first read error handling
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US Patent 11049578 Non-volatile memory with program verify skip
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US Patent 10629272 Two-stage ramp up of word line voltages in memory device to suppress read disturb
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US Patent 11189337 Multi-stage voltage control for peak and average current reduction of open blocks
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US Patent 8982637 Vread bias allocation on word lines for read disturb reduction in 3D non-volatile memory
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US Patent 9361993 Method of reducing hot electron injection type of read disturb in memory
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Patent Inventor Names
Xiang Yang
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Jiacen Guo
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Xiaochen Zhu
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
11881271
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Patent Primary Examiner
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Jay W. Radke
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CPC Code
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G11C 16/08
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G11C 16/26
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G11C 16/0483
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G11C 16/3427
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