US Patent 11887657 Amplifier circuit, control method, and memory

The present disclosure relates to an amplifier circuit, a control method, and a memory, including: a sensing amplification circuit, including a readout node, a complementary readout node, a first node, and a second node; an isolation circuit, coupled to the readout node, the complementary readout node, a bit line, and a complementary bit line, wherein the isolation circuit is configured to couple the readout node to the bit line and the complementary readout node to the complementary bit line at a sensing amplification stage; an offset cancellation circuit, coupled to the bit line, the complementary bit line, the readout node, and the complementary readout node, wherein the offset cancellation circuit is configured to couple the bit line to the complementary readout node and the complementary bit line to the readout node at an offset cancellation stage; and a processing circuit, coupled to the offset cancellation circuit.