US Patent 11894045 Processing in memory implementing VLIW controller

An example apparatus includes a processing in memory (PIM) capable device having an array of memory cells and sensing circuitry coupled to the array. The PIM capable includes a row address strobe (RAS) component selectably coupled to the array. The RAS component is configured to select, retrieve a data value from, and input a data value to a specific row in the array. The PIM capable device also includes a RAS manager selectably coupled to the RAS component. The RAS manager is configured to coordinate timing of a sequence of compute sub-operations performed using the RAS component. The apparatus also includes a source external to the PIM capable device. The RAS manager is configured to receive instructions from the source to control timing of performance of a compute operation using the sensing circuitry.