US Patent 11907043 Adaptive wake-up for power conservation in a processor

A processor can include various processing pipelines that perform different data processing operations, with different pipelines having dedicated logic and memory circuits. A power management circuit can determine when to supply power to various pipelines, including the logic and memory circuits of the various pipelines, depending on a current operating mode of the processor. When a memory circuit transitions to a lower power state such as a sleep state, data can be saved to a different memory circuit that is not transitioning to a lower power state, and when the memory circuit is powered up again, the data can be restored from the different memory circuit.