US Patent 11908512 3D NAND flash memory devices and related electronic systems

A microelectronic device comprises local digit line structures, global digit line structures, source line structures, sense transistors, read transistors, and write transistors. The local digit line structures are coupled to strings of memory cells. The global digit line structures overlie the local digit line structures. The source line structures are interposed between the local digit line structures and the global digit line structures. The sense transistors are interposed between the source line structures and the global digit line structures, and are coupled to the local digit line structures and the source line structures. The read transistors are interposed between and are coupled to the sense transistors and the global digit line structures. The write transistors are interposed between and are coupled to the global digit line structures and the local digit line structures. Additional microelectronic devices, memory devices, and electronic systems are also described.