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US Patent 11908923 Low-resistance top contact on VTFET
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Patent
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Date Filed
September 21, 2020
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Date of Patent
February 20, 2024
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Patent Application Number
17026451
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Patent Citations
US Patent 9653575 Vertical transistor with a body contact for back-biasing
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US Patent 9773708 Devices and methods of forming VFET with self-aligned replacement metal gates aligned to top spacer post top source drain EPI
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US Patent 9859166 Vertical field effect transistor having U-shaped top spacer
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US Patent 9859421 Vertical field effect transistor with subway etch replacement metal gate
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US Patent 10361315 Method and apparatus of fabricating source and drain epitaxy for vertical field effect transistor
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US Patent 9899515 Fabrication of a pair of vertical fin field effect transistors having a merged top source/drain
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US Patent 10833173 Low-resistance top contact on VTFET
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US Patent 7241655 Method of fabricating a vertical wrap-around-gate field-effect-transistor for high density, low voltage logic and memory array
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US Patent 9530866 Methods of forming vertical transistor devices with self-aligned top source/drain conductive contacts
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Patent Inventor Names
Hemanth Jagannathan
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Su Chen Fan
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Hari Prasad Amanapu
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Christopher J. Waskiewicz
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Patent Jurisdiction
United States Patent and Trademark Office
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Patent Number
11908923
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Patent Primary Examiner
Mark V. Prenty
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CPC Code
H01L 29/66666
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H01L 21/823487
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