US Patent 11910609 Semiconductor memory device

A semiconductor memory device includes a substrate including a first to a fourth region, first conductive layers from the first to second region, second conductive layers from the fourth to second region, third conductive layers from the first to third region, fourth conductive layers from the fourth to third region, a first semiconductor column opposed to the first and third conductive layers in the first region, a second semiconductor column opposed to the second and fourth conductive layers in the fourth region, first and second contacts connected to the first and the second conductive layers in the second region, third and fourth contacts connected to the third and fourth conductive layers in the third region, first wirings connected to the first and second contacts in the second region, and second wirings connected to the third and fourth contacts in the third region.