Patent attributes
An electrostatic discharge clamp is shown, which includes a clamping circuit, a driving circuit, a capacitor and resistor network, and a bias circuit. The clamping circuit has a plurality of transistors connected in a cascode configuration. The driving circuit is coupled to the gates of the transistors of the clamping circuit. The capacitor and resistor network introduces an RC delay in response to an electrostatic discharge event to control the driving circuit to turn on the transistors of the clamping circuit for electrostatic discharging. The bias circuit biases the driving circuit to turn off the transistors of the clamping circuit when the capacitor and resistor network does not detect the electrostatic discharge event.