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US Patent 11922035 Read-disturb-based read temperature adjustment system
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Patent
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Date Filed
January 21, 2022
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Date of Patent
March 5, 2024
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Patent Application Number
17580756
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Patent Citations
US Patent 8910000 Program-disturb management for phase change memory
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US Patent 9165647 Multistage memory cell read
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US Patent 11177014 Global-local read calibration
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US Patent 10346312 Variable-size flash translation layer
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US Patent 11586385 Techniques for managing writes in nonvolatile memory
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US Patent 7188282 Tamper resistant shadow memory
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US Patent 7844876 Temperature sampling in electronic devices
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Patent Inventor Names
Walter A. O'Brien, III
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Ali Aiouaz
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Leland W. Thompson
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Patent Jurisdiction
United States Patent and Trademark Office
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Patent Number
11922035
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Patent Primary Examiner
Daniel D Tsui
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CPC Code
G06F 3/0659
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G06F 3/0679
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G06F 3/0619
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G06F 3/064
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