US Patent 11923363 Semiconductor structure having bottom isolation and enhanced carrier mobility

Illustrative embodiments provide techniques for fabricating semiconductor structures having bottom isolation and enhanced carrier mobility for both nFET and pFET devices. For example, in one illustrative embodiment, a semiconductor structure includes a semiconductor substrate, a first dielectric layer disposed on the semiconductor substrate, a bottom source/drain region disposed on the first dielectric layer and isolated from the semiconductor substrate by the first dielectric layer, a second dielectric layer disposed on the bottom source/drain region and a top source/drain region disposed on the second dielectric layer and isolated from the bottom source/drain region by the second dielectric layer. The bottom source/drain region comprises a compressive pFET epitaxy and the top source/drain region comprises a tensile nFET epitaxy.