Patent attributes
A delay-compensating power management integrated circuit (PMIC) is provided. The PMIC includes a target voltage circuit configured to generate a target voltage that is utilized for generating a time-variant voltage to amplify an analog signal. The target voltage is generated based on a time-variant envelope of the analog signal but lags behind the time-variant envelope by a temporal delay(s) due to an inherent processing delay in the target voltage circuit. In this regard, a voltage processing circuit is provided in the target voltage circuit to generate a modified target voltage that is time-adjusted relative to the target voltage to substantially offset the temporal delay(s). By generating the time-variant voltage based on the modified target voltage, the time-variant voltage can be better aligned with the time-variant envelope of the analog signal, thus helping to reduce amplitude distortion when amplifying the analog signal.
