Patent attributes
A DCO is configured such that, during a period in which a selection signal is asserted, a ring oscillator is formed so as to oscillate at a frequency that corresponds to a control code, and such that, during a period in which the selection signal SEL is negated, an injection edge based on a reference clock can be injected. During the startup period of a PLL circuit, a controller repeats a cycle including (i) a process in which the selection signal is asserted so as to oscillate the DCO, and phase comparison is made between an oscillator clock and the reference clock, and (ii) a process in which the selection signal is negated so as to stop the DCO, and the control code is updated by a binary search based on a result of the phase comparison.
