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US Patent 11928020 Memory error detection

Patent 11928020 was granted and assigned to Rambus on March, 2024 by the United States Patent and Trademark Office.

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
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Current Assignee
Rambus
Rambus
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Date Filed
January 10, 2023
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Date of Patent
March 12, 2024
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Patent Applicant
Rambus
Rambus
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Patent Application Number
18095341
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Patent Citations
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US Patent 6941493 Memory subsystem including an error detection mechanism for address and control signals
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US Patent 6845472 Memory sub-system error cleansing
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US Patent 6851081 Semiconductor memory device having ECC type error recovery circuit
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US Patent 6883130 Enhanced and adaptive error detection in digital communications
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US Patent 6909758 Systems and methods for decoding data blocks
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US Patent 6912682 Signal processor for correcting and detecting errors
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US Patent 7624298 Memory card, data processor, memory card control method and memory card setting
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US Patent 7657783 Apparatus and computer program product for testing ability to recover from cache directory errors
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US Patent 7836386 Phase shift adjusting method and circuit
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US Patent 7831882 Memory system with error detection and retry modes of operation
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•••
Patent Inventor Names
Craig E. Hampel
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Ian Shaeffer
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
11928020
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Patent Primary Examiner
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Joshua P Lottich
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CPC Code
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G06F 11/1004
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G06F 11/0703
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H03M 13/09
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G06F 11/1679
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G06F 11/073
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